1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to a delta-sigma analog-to-digital converter having a dither controlled based on detected quantizer code patterns.
2. Background of the Invention
Delta-sigma modulators are in widespread use in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), in which they provide very linear behavior and simple implementation due to the reduced number of bits used in the analog signal comparison. Delta-sigma modulators can be implemented with a high level of control of the frequency distribution of “quantization noise”, which is the difference between the ideal output value of the modulator as determined by the input signal and the actual output of the modulator provided by a quantizer. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable.
The delta-sigma modulator based ADC typically includes an analog loop filter that receives an input signal and a quantizer that converts the analog output of the loop filter to a digital representation. A feedback signal provided from the output of the quantizer is provided to the analog loop filter to close the loop such that the average output of the quantizer is equal to the value of the input signal. The output of the quantizer is then filtered by a low-pass digital filter having a large number of taps, in order to provide an accurate conversion result from the quantizer output, which typically includes hundreds of values per conversion cycle.
Dither is often introduced to the analog loop filter or directly into the quantizer, in order to ensure that the signal level being quantized has sufficient changes so that the quantizer output is constantly changing and therefore providing the above-described noise shaping operation. In precision ADCs, it is desirable to under-dither, that is, to provide a peak-to-peak dither signal or value that represents less than a level that would generate a code change from the quantizer. Under-dithering provides for the greatest ADC dynamic range, as addition of the dither signal limits the range of signal values that in combination with the worst-case noise-shaping feedback and dither conditions (i.e., when the feedback, dither and input signal provide the same polarity and are of maximum magnitude when referred to the input to the quantizer) cause instability due to saturation at the quantizer output code range extremes.
However, under-dithering has a disadvantage in that when the sum of the feedback and input signal as referred to the input of the quantizer is static, the code from the output of the quantizer does not change unless the contribution of the dither signal or value is sufficient to cause the quantizer to change level. The result is a long sequence of unchanging quantizer output values, which causes the noise-shaping loop to temporarily become “stuck” in what is essentially an open-loop state. Normally, the very infrequent occurrence of such unchanging sequences is tolerable in ADC converters in exchange for the precision benefit gained from under-dithering. However, if the converter is reset, the production of such a unchanging sequence is more probable.
Therefore, it would be desirable to provide an under-dithered delta-sigma modulator that has a reduced frequency of stuck code sequences. It would further be desirable to provide such a delta-sigma modulator that can be reset without generating an excessive number of unchanging quantizer code sequences.